With the advent of portable and small-sized computing systems, including the new trend of systems-on-a-chip computing, power consumption has recently emerged as a focal point in many research projects and commercial systems. These projects typically address the issue of minimizing power consumption in a given platform, which usually translates into longer battery life. Current power-efficient systems have management functions that can be invoked to turn off some system components, or to choose between different power states for each component. Advance Power Management (APM) and Advanced Configuration & Power Interface (ACPI) are standard interfaces that provide the applications with some power management functionality. Recent research has demonstrated that further reduction in power consumption can be accomplished by dynamic voltage/frequency scaling, compiler techniques, and selective use of alternative algorithms.
In our proposed research we consider the goal of minimizing power consumption while still meeting deadlines. Our approach for achieving the power/deadlines objective is to develop new schemes for power-aware real-time systems, including scheduling algorithms, power control of memory resources, speed control of CPUs, and dynamic power monitoring and mode changes. The new schemes have to be integrated into the appropriate components of the system. For example, power control of memory resources requires new hardware capabilities, corresponding operating system support, and algorithms for taking advantage of these mechanisms.
Our research also recognizes the problem of evaluating the effectiveness of power management policies and architectures. Previous research has shown that the inability to produce repeatable measurements impedes progress in developing new power management schemes. We propose a new methodology for evaluating power-aware systems, which relies on extending a full system emulator developed at IBM for the PowerPC architecture. The extensions will measure power consumption of each of the devices at the lowest-possible level (e.g., for a CPU, the power consumption of an instruction), and provide an interface to the higher layers of our proposed architecture for querying and changing specific power parameters of the system. We will call this new emulator Power-SimOS. There are several benefits of this methodology. It speeds up development of our proposed scheduling algorithms and provides a systematic evaluation procedure. Also, it allows us to model hardware facilities that do not exist today, and evaluate these models to guide future hardware implementations.
The SimOS emulator for PowerPC is faithful enough to allow IBM's standard AIX (Unix) operating system to run unmodified on this extended SimOS. We will implement our power-management algorithms in a middleware that interfaces both with AIX (for regular operating system functions) and directly with Power-SimOS (for power management functions). This implementation will allow us to explore new power management techniques taking advantage of the state-of-the-art hardware. By allowing the middleware to directly access the new power capabilities of Power-SimOS, we are creating a power management virtual interface without actually changing the operating system. Given that some of our schemes require services beyond the ones provided by ACPI, our virtual interface will provide a superset of the primitives provided by ACPI.
Research funded by DARPA / ITO Power-Aware Computing and Communication (PACC) program.